Diffusion barrier and method of formation thereof

ABSTRACT

A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of co-pending U.S. patentapplication Ser. No. 13/688,229, filed on Nov. 29, 2012, which is acontinuation application of U.S. patent application Ser. No. 12/144,652,filed on Jun. 24, 2008, now U.S. Pat. No. 8,324,031, the disclosures ofwhich are herein incorporated by reference in their entireties.

FIELD OF THE INVENTION

The present invention relates to diffusion barriers and to a method offorming a diffusion barrier. In particular but not exclusively theinvention relates to a diffusion barrier in an integrated circuit deviceand a method of forming a diffusion barrier in an integrated circuitdevice.

BACKGROUND

Diffusion of dopant atoms and other atoms in integrated circuit (IC)structures is responsible for a number of problems associated with thefabrication and long term stability of IC structures. For example,electrical characteristics of static random access memory (SRAM)structures are adversely affected by lateral diffusion in polysilicon ofdopant such as phosphorus from strongly n+ doped regions. This causesN+/P+ junctions between NFET and PFET devices to shift towards the PFETdevice.

In order to ameliorate the problem, a shallower n+ pre-doped implant anda smaller N+ implanted area have been adopted. However, substantialdiffusion of dopant still occurs during subsequent thermal processingsuch as polysilicon reoxidation processes and rapid thermal annealing(RTA).

Furthermore, diffusion of extrinsic dopant and source/drain dopant intothe channel region can occur, again resulting in an adverse effect onelectrical characteristics of the structure. For example, the thresholdvoltage at which a channel region of a transistor device begins toconduct typically reduces with increased amounts of lateral diffusion ofextrinsic and source/drain dopant. Consequently, sub-threshold leakagecan be increased by several orders of magnitude.

To mitigate this problem, a reduced dose of dopant may be applied whenforming a halo region, and a lower temperature employed in the course ofrapid thermal annealing of the structure. However, such measures mayintroduce further problems such as gate induced drain leakage (GIDL) anda lack of dopant activation.

SUMMARY

A method of forming a device or a semiconductor device is disclosed. Themethod includes providing a structure or substrate having first andsecond regions. The method further includes forming a diffusion barrierbetween at least a portion of the first and second regions. Thediffusion barrier comprises cavities that reduce diffusion of elementsbetween the first and second regions.

In another aspect, a device that comprises a structure having first andsecond regions is presented. The device further includes a diffusionbarrier disposed between at least a portion of the first and secondregions. The diffusion barrier comprises cavities that reduce diffusionof elements between the first and second regions.

These and other objects along with advantages and features of thepresent invention herein disclosed, will become apparent throughreference to the following description and the accompanying drawings.Furthermore, it is to be understood that the features of the variousembodiments described herein are not mutually exclusive and can exist invarious combinations and permutations.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like reference characters generally refer to the sameparts throughout the different views. Also, the drawings are notnecessarily to scale, emphasis instead generally being placed uponillustrating the principles of the invention. Various embodiments of thepresent invention are described with reference to the followingdrawings, in which:

FIGS. 1 to 4 show structures formed during a process of forming adiffusion barrier in a polysilicon layer according to an embodiment ofthe invention.

FIGS. 5 to 9 show structures formed during a process of forming adiffusion barrier in a substrate according to an embodiment of theinvention.

FIGS. 10 to 13 show structures formed during a process of forming aMOSFET device having a self-aligned diffusion barrier below a gateregion of the device according to an embodiment of the invention.

FIGS. 14 to 16 show structures formed during a process of forming aMOSFET device having self-aligned diffusion barriers below source anddrain regions of the device according to an embodiment of the invention.

DETAILED DESCRIPTION

FIG. 1 is a schematic illustration in cross-section of a structure 100formed during a process of fabricating a semiconductor device, such as astatic random access memory (SRAM) device. Forming other types ofdevices or structures are also useful.

The structure has a silicon substrate 102 having a plurality of, forexample, P-type doped well regions (P-wells) 104 and a plurality ofN-type doped well regions (N-wells) 106. Respective P-wells 104 andN-wells 106 are separated by shallow trench isolation (STI) regions 108.

The substrate 102 has a layer of a gate dielectric medium 110 formedthereover. In the embodiment of FIG. 1, the layer of gate dielectricmedium 110 is a layer of nitrided silicon oxide. In some embodiments,the layer of gate dielectric medium 110 is silicon oxide or any othersuitable gate dielectric medium. In some embodiments, layer 110 isformed from a high dielectric constant (“high-k”) gate dielectricmaterial.

The layer of gate dielectric medium 110 has a gate electrode layer 120formed thereover. The gate electrode layer, for example, comprisespolysilicon. In the embodiment of FIG. 1, the polysilicon layer 120 isaround 800 Å in thickness. Other thicknesses are also useful. In someembodiments, the thickness is in the range from around 600 Å to around2000 Å.

Other substrate materials are also useful. Other thicknesses ofpolysilicon layer 120 are also useful. Other layer materials are alsouseful for forming a gate electrode instead of or in addition topolysilicon.

FIG. 2 shows the structure of FIG. 1 during a process of implanting animplant medium into the polysilicon layer 120 to form an implant region132. In one embodiment, the implant region 132 spans or substantiallyspans the thickness of the polysilicon layer 120.

In some embodiments, the implant region 132 is arranged to partiallyspan the thickness of the polysilicon layer 120. For example,non-implant regions without implant medium therein can be provided aboveand/or below the implant region 132. Other configurations of implant andnon-implant regions are also useful. The non-implant regions canfacilitate the formation of metal silicide therein.

In the embodiment of FIG. 2, the implant medium comprises He atoms.Other implant media or combinations are also useful. For example,hydrogen and/or argon atoms can be used. The implant medium should havea gaseous state at room temperature (e.g., about 20° C.) and a pressureof about 1 bar (100 kPa).

As shown in FIG. 2, a mask member 150 is provided between the structure100 and a source of He atoms in spaced apart relationship with a surface122 of the polysilicon layer 120. In some embodiments, the mask member150 is provided in contact with the surface 122. In some embodiments themask member 150 is formed directly on the surface 122.

In the embodiment of FIG. 2, the mask member has an opening arranged toallow exposure to incident He atoms of a portion of the polysiliconlayer 120. The portion exposed is that located above STI region 108Aseparating each P-well 104 from an N-well 106.

In one embodiment, the implant conditions are established such thatimplantation of atoms occurs to a depth in the range of from around atleast 30% to around 70% of the thickness of the polysilicon layer 120.In some embodiments, the range of depth is around half of the thicknessof the polysilicon layer 120. Other implant depths may also be useful.

In the embodiment of FIG. 2, the mask member 150 is a mask used todefine STI regions 108A of the structure. Other mask members are alsouseful such as masks used to define RX regions.

FIG. 3 shows the structure of FIG. 2 following an annealing process. Theannealing causes implant medium to expand, forming cavities 134 in theimplant region 132. The structure, for example, is annealed at atemperature of 800° C. for a period of from around 10 minutes to severalhours. The annealing can be conducted in an inert gas atmosphere such asargon, nitrogen, or any other suitable inert gas. It will be appreciatedthat the size of the cavities formed by annealing of the structure willdepend on the duration of the annealing process.

Other annealing temperatures are also useful. In some embodiments,annealing is performed at a temperature in the range of from around 800°C. to around 1000° C. In some embodiments, the annealing process isperformed for a period of time sufficient to form cavities 134 in thepolysilicon layer 120 having a size in the range of from around 2 nm toaround 60 nm. In some embodiments, portions of the polysilicon layer 120in which cavities 134 form provide a barrier 135 to diffusion of dopantatoms in the polysilicon layer 120 from one side of the barrier 135 tothe other.

In the embodiment of FIG. 3, the layer of polysilicon is around 800 Å inthickness and the cavities have a size in the range of from around 5 nmto around 10 nm.

It is to be understood that if the cavities 134 are formed to be toolarge, the polysilicon line may fail. For example, the polysilicon linemay disintegrate due to fracture of polysilicon.

It is also to be understood that the depth at which the cavities 134 maybe formed is dependent on the depth of the structure to which theimplant medium is implanted.

FIG. 4 shows the structure of FIG. 3 during a process of implantingdopants in a portion of the gate electrode layer 120. For example,n-type dopants are implanted into a portion of the polysilicon layer 120overlying the P-well 104. A mask member 160 is provided between thepolysilicon layer 120 and a source of n-type dopant thereby to shieldthe n-type dopant source from the portion of the polysilicon layer 120overlying N-wells 104 and the portion of polysilicon layer 120containing barrier 135. Implanting other types of dopants and/or inother portions of the gate electrode layer is also useful.

In the embodiment of FIG. 4, the n-type dopant comprises arsenic atoms.Other dopant atoms are also useful such as phosphorus atoms or any othersuitable n-type dopant. The n-type dopant atoms are implanted to form ann+ predoped region 140.

The gate electrode and dielectric layers can be patterned to form gateconductors. In one embodiment, the gate electrode and dielectric layersare patterned to form a gate conductor passing through the N well and Pwell. Additional processes for completing transistors can be performed.

The embodiment of FIG. 4 has the feature that an amount of n-type dopantatoms that diffuse from the n+ predoped region 140 beyond the barrierregion 135 is substantially reduced compared with a structure in whichno barrier region 135 is provided.

FIG. 5 shows a structure 200 having a substrate 202 having a layer of abuffer medium 210 formed thereover. In the embodiment of FIG. 5, thebuffer medium comprises nitrided silicon oxide. Other buffer media arealso useful including silicon oxide and high-k gate dielectricmaterials.

In the structure of FIG. 5, an implant region 232 has been formed in thesubstrate 202 by implantation of an implant medium. The implant medium,for example, comprises He atoms. Other types of implant media, asdescribed, are also useful. The implant region 232 is formed at a depthsuch that a MOSFET device may be formed above the implant region 232.The depth is also such that diffusion of dopant atoms away from theMOSFET device will be sufficiently limited by the implant region 232 toprevent substantial deterioration in device performance.

For structures formed using 45 nm feature size technologies, an implantenergy in the range of from around 4 keV to around 7 keV is used, and adose of from around 10¹⁴ to 5×10¹⁵ cm⁻² is provided.

FIG. 6 shows the structure of FIG. 5 following a process of forming STIregions 208. The STI regions 208 are formed by a conventionalfabrication process for STI formation.

FIG. 7 shows the structure of FIG. 6 following a process of annealingthe structure to form cavities 234 in the implant region 232 thereby toform a barrier region 235. In the embodiment of FIG. 7, the structure isannealed at a temperature of 800° C. for a period of between 10 minutesand several hours in an inert gas atmosphere. It is to be understoodthat in some embodiments the size of the cavities 234 formed uponannealing will depend upon the duration of the annealing process.

FIG. 8 shows the structure of FIG. 7 following a process of forming agate dielectric layer 210 and subsequently a gate electrode 270 of atransistor, such as a MOSFET device, over the substrate 202. In theembodiment of FIG. 8, the gate dielectric layer 210 is formed fromnitrided silicon oxide. Other gate dielectric media are useful includingsilicon oxide and high-k gate dielectric materials.

The gate electrode 270 is formed from polysilicon by a process ofblanket layer formation followed by a process of patterning and etching.

FIG. 9 shows the structure of FIG. 8 following a process of formingfirst spacer elements 272 on sidewalls of the gate electrode 270followed by formation of source and drain halo regions 282, 262respectively in the substrate 202 by implantation of dopant atoms.

Subsequently, second spacer elements 274 have been formed on the firstspacer elements 272 and deep source and drain regions 284, 264respectively formed by implantation of dopant atoms.

The structure of FIG. 9 provides a transistor 290, such as a MOSFETdevice located between STI regions 208. The structure has a barrierlayer 235 formed from cavities 234 that span a distance from one STIregion 208 to another adjacent STI region 208. This feature reduces anamount of diffusion of dopant atoms such as those dopant atoms formingthe source and drain regions 284, 264 to portions of the substrate 202away from the device 290. This results in a reduction in an extent towhich device performance is degraded by diffusion of dopant atoms duringa process of fabricating an integrated circuit comprising barrier layersaccording to some embodiments of the invention.

FIG. 10 shows a structure 300 having a substrate 302 having STI regions308 formed therein. A mask member 350, for example, having a layer ofsilicon oxide 352 and a layer of silicon nitride 354 thereover has beenformed over the substrate 302. The layer of silicon oxide is formed tohave a thickness of around 5-10 nm whilst the layer of silicon nitrideis formed to have a thickness of around 20-80 nm. Other materials areuseful for forming the mask member 350.

Other thicknesses of layers comprised by the mask member 350 are alsouseful. In some embodiments, the mask member is formed from apolymer-based photoresist material. Other photoresist materials are alsouseful.

FIG. 11 shows the structure 300 of FIG. 10 following a process ofetching the mask member 350 to expose a portion of the surface 302A ofthe substrate 302 over which a gate electrode is to be formed.Implantation of an implant medium into the substrate 302 has also beenperformed whereby an implant region is formed below a portion of thesubstrate that will form a channel region of the device. The implantregion is provided between regions of the device in which source anddrain implants, respectively, are to be made in order that thesubsequently formed cavities will suppress lateral diffusion ofimplanted atoms.

In some embodiments, implantation of the implant medium is performed atan energy in the range of from around 2 keV to around 100 keV, and at adose of around 1×10¹³ to around 5×10¹⁵ cm⁻².

Following implantation, the structure 300 is annealed at a temperatureof 800° C. to form cavities 334 in the substrate 302 in a similar mannerto that described above with respect to other embodiments of theinvention. Other temperatures are also useful, as discussed in respectof other embodiments of the invention.

The structure is configured whereby the cavities provide a diffusionbarrier 335 in a region of the substrate immediately below a channelregion 380 of the structure.

FIG. 12 shows the structure 300 of FIG. 11 following a process offorming a gate dielectric layer 310 over the exposed portion 302A of thesurface of the substrate 302. In the embodiment of FIG. 12, the gatedielectric is a layer of silicon oxide. Other gate dielectric materialsare useful in addition to or instead of silicon oxide. For example, ahigh-k gate dielectric material such as hafnium oxide or any othersuitable material may be used.

In a subsequent step, a blanket layer of polysilicon 370 as shown inFIG. 13 is formed over the structure and an etchback process performedto define a gate electrode 370 above the gate dielectric layer 310.

FIG. 13 shows the structure of FIG. 12 following a process of removal ofthe nitride layer 354 and formation of first spacer elements 372 onsidewalls of the gate electrode 370. Source and drain halo regions 382,362 are formed by implantation of dopant atoms. Second spacer elements374 are formed on the first spacer elements 372 and deep source anddrain regions 384, 364 formed by implantation of dopant atoms.

The resulting structure 300 of FIG. 13 provides a MOSFET device having aself-aligned diffusion barrier 335 below the channel region 380 of thestructure that is provided by the presence of cavities 334 in thesubstrate. The cavities 334 may also be referred to as ‘microcavities’334. As can be seen from FIG. 13, the diffusion barrier 335 has beenformed below the channel region 380 at a depth corresponding to that oflower portions of the deep source and drain regions 384, 364.

FIG. 14 shows a structure 400 having a substrate 402 having STI regions408 formed therein and a layer of a gate dielectric material 410 formedthereover. In the embodiment of FIG. 14, the gate dielectric material issilicon oxide. Other gate dielectric materials are also useful, asdiscussed above with respect to other embodiments of the invention.

A gate electrode 470 has been formed over a channel region 480 of thestructure. In the embodiment of FIG. 14, the gate electrode 470 isformed from polysilicon. Other materials are also useful. First spacerelements 472 have been formed on sidewalls of the gate electrode 470 anda capping layer 473 provided over the gate electrode 470. In theembodiment of FIG. 14, the first spacer elements 472 and capping layer473 are formed from silicon nitride. Other materials are also useful.

Implant regions 432 have been formed in the substrate 402 below sourceand drain regions of the structure by implantation of an implant mediumas described above with respect to other embodiments. The capping layer473 and first spacer elements 472 mask the channel region 480 of thesubstrate 402 from the implant medium in a similar manner to the maskmember 350 of the embodiment of FIG. 10.

FIG. 15 shows the structure 400 of FIG. 14 following a process ofannealing the structure 400 to form barrier regions 435 each comprisinga plurality of cavities 434. Implant conditions are optimised such thatthe barrier regions 435 are formed below regions of the substrate whererespective source and drain regions are to be formed.

It will be appreciated that implantation of source and drain dopantatoms may be performed before or after formation of the barrier regions435. In the embodiment of FIG. 15, the source and drain dopant atoms areimplanted after formation of the barrier regions 435.

In the embodiment of FIG. 15, the implant energy is in the range of fromaround 2 keV to around 100 keV depending upon the depth to which thesource and drain regions are to be formed, at a dose of around 1×10¹³ toaround 5×10¹⁵ cm⁻².

FIG. 16 shows the structure 400 of FIG. 15 following a process ofimplanting a dopant medium to form source and drain halo regions 482,462 followed by formation of second spacer elements 474 over the firstspacer elements 472. Implantation of a dopant medium is then performedto form deep source and drain regions 484, 464.

In embodiments of the invention in which FET devices are formed, thedopant medium used to form source and drain halo regions and deep sourceand drain regions may be an n-type dopant medium in the case of theformation of an NFET device or a p-type dopant medium in the case offormation of a PFET device.

It is understood that various embodiments of diffusion barriers can becombined, such as any two or more embodiments. For example, a diffusionbarrier below the channel (as shown in FIG. 13) can be combined withdiffusion barriers below the source/drain regions (as shown in FIG. 15)or the diffusion barrier below the channel can be combined with thediffusion barrier in the substrate below the transistor (as shown inFIG. 9). Furthermore, these embodiments can be combined with the barrierin a portion of the gate electrode (as shown in FIG. 3). Theimplantation can be performed by separate processes while the annealingcan be combined. Other process sequences or combinations are alsouseful.

Some embodiments of the invention have the advantage that electricalproperties of transistor devices of an integrated circuit structure areimproved relative to integrated circuit structures not having diffusionbarriers according to one or more embodiments of the invention. This isat least in part because in some embodiments of the invention an amountof diffusion of dopant atoms from one region of a device structure toanother region is substantially reduced.

Throughout the description and claims of this specification, the words“comprise” and “contain” and variations of the words, for example“comprising” and “comprises”, means “including but not limited to”, andis not intended to (and does not) exclude other moieties, additives,components, integers or steps.

Throughout the description and claims of this specification, thesingular encompasses the plural unless the context otherwise requires.In particular, where the indefinite article is used, the specificationis to be understood as contemplating plurality as well as singularity,unless the context requires otherwise.

Features, integers and characteristics described in conjunction with aparticular aspect, embodiment or example of the invention are to beunderstood to be applicable to any other aspect, embodiment or exampledescribed herein unless incompatible therewith.

The invention may be embodied in other specific forms without departingfrom the spirit or essential characteristics thereof. The foregoingembodiments, therefore, are to be considered in all respectsillustrative rather than limiting the invention described herein. Scopeof the invention is thus indicated by the appended claims, rather thanby the foregoing description, and all changes that come within themeaning and range of equivalency of the claims are intended to beembraced therein.

What is claimed is:
 1. A method of forming a device comprising:providing a substrate; forming a gate structure over the substrate;forming first and second diffusion regions in the substrate on opposedsides of the gate structure; and forming a diffusion barrier havingcavities in the substrate in between the first and second diffusionregions, wherein the diffusion barrier is formed immediately below achannel region which is disposed below the gate structure.
 2. The methodof claim 1 wherein the diffusion barrier is formed at a depthcorresponding to lower portions of the first and second diffusionregions.
 3. The method of claim 1 wherein forming the diffusion barriercomprises: providing a mask on top of the substrate, the mask comprisesa cavity that exposes a portion of a top surface of the substrate ofwhich the gate structure is to be formed; implanting an implant mediumin the portion exposed by the cavity to form an implant region below aportion of the substrate which forms the channel region; and annealingthe implant region to form the cavities.
 4. The method of claim 3wherein the mask comprises a silicon oxide layer and a silicon nitridelayer over the silicon oxide layer.
 5. The method of claim 3 wherein themask comprises a polymer-based photoresist material.
 6. The method ofclaim 3 wherein the implant medium comprises He, hydrogen, argon atomsor a combination thereof.
 7. The method of claim 3 wherein implantingthe implant medium is performed at an energy in the range of from around2 keV to around 100 keV and at a dose of around 1×10¹³ to around 5×10¹⁵cm⁻².
 8. The method of claim 3 wherein forming the gate structurecomprises: forming a gate dielectric layer over the exposed portion ofthe top surface of the substrate; blanket depositing a gate electrodelayer over the mask; and performing an etch back process to form a gateelectrode over the gate dielectric layer in the cavity.
 9. The method ofclaim 8 comprises: removing the mask; and forming spacer elements onsidewalls of the gate structure, wherein the first and second diffusionregions are source and drain regions which are formed after forming thespacer elements and the diffusion barrier.
 10. A method of forming adevice comprising: providing a substrate; forming a gate structure overthe substrate; forming first and second diffusion regions in thesubstrate on opposed sides of the gate structure; and forming at least afirst diffusion barrier having cavities in the substrate in between thefirst and second diffusion regions, wherein the first diffusion barrieris formed immediately below a channel region which is disposed below thegate structure.
 11. The method of claim 10 wherein the first diffusionbarrier is formed at a depth corresponding to lower portions of thefirst and second diffusion regions.
 12. The method of claim 10 whereinthe at least a first diffusion barrier reduces out-diffusion of dopantsfrom the first and second diffusion regions.
 13. The method of claim 10wherein forming the at least a first diffusion barrier comprises formingsecond and third diffusion barriers, wherein the second and thirddiffusion barriers are separated from each other and are formedimmediately adjacent to bottom ends of the first and second diffusionregions.
 14. The method of claim 10 comprising: forming a plurality ofshallow trench isolation (STI) regions in the substrate; and whereinforming the at least a first diffusion barrier comprises forming asecond diffusion barrier, wherein the second diffusion barrier is formedimmediately adjacent to bottom ends of the first and second diffusionregions and the second diffusion barrier spans a substantial distancefrom one STI region to another adjacent STI region.
 15. A devicecomprising: a substrate; a gate structure over the substrate; first andsecond diffusion regions disposed in the substrate on opposed sides ofthe gate structure; and at least a first diffusion barrier havingcavities disposed in the substrate in between the first and seconddiffusion regions, wherein the first diffusion barrier is disposedimmediately below a channel region which is disposed below the gatestructure.
 16. The device of claim 15 wherein the first diffusionbarrier is formed at a depth corresponding to lower portions of thefirst and second diffusion regions.
 17. The device of claim 15 whereinthe first and second diffusion regions are source and drain regions. 18.The device of claim 15 wherein the at least a first diffusion barriercomprises a second diffusion barrier, wherein the second diffusionbarrier is disposed immediately adjacent to a bottom end of the first orsecond diffusion region.
 19. The device of claim 15 wherein the at leasta first diffusion barrier comprises second and third diffusion barriers,wherein the second and third diffusion barriers are separated from eachother and are disposed immediately adjacent to bottom ends of the firstand second diffusion regions.
 20. The device of claim 15 comprising: aplurality of shallow trench isolation (STI) regions in the substrate;and wherein the at least a first diffusion barrier comprises a seconddiffusion barrier, wherein the second diffusion barrier is disposedimmediately adjacent to bottom ends of the first and second diffusionregions and the second diffusion barrier spans a substantial distancefrom one STI region to another adjacent STI region.